VF-TLP and CDM differences
VF-TLP can be a guide to CDM failure levels, and provide a lot of understanding of a circuit’s operation during CDM stressing, but simple correlations between VF-TLP failure current level and CDM withstand voltage levels are difficult to establish.
How well will VF-TLP results predict CDM testing performance?
CDM is one of the two ESD tests used to qualify new ICs for ESD sensitivity; the other being human body model (HBM). CDM is a stress method that replicates the rapid discharge through an IC pin that can be encountered in the real world when an IC has been charged relative to its immediate environment. Handling equipment, friction with shipping materials, or even airflow over an IC, can slowly impart a charge. Subsequent handling, especially by robotic means, can cause a spark to ground through an IC pin. CDM provides a known stress to the individual pins of an IC. The IC is precharged to a specific voltage, and then a grounded needle is brought close to a pin or ball, typically producing a very fast ESD spark discharge from that pin or ball to ground. All pins of several ICs are stressed by spark discharges from a set of precharged voltages of both polarities. Then the ICs are tested with automatic test equipment (ATE) to determine if the ICs are still fully functional or if they have been damaged. The information from a CDM test is pass or fail at a stress voltage. The highest passing voltage is the ESD withstanding level and is used to classify the IC per standard test methods such as ANSI/ESDA/JEDEC JS-002-2014
Very fast transmission line pulsing (VF-TLP) is often used to study the operation of IC protection structures under stresses similar to what is encountered in the charged device model (CDM) test. But TLP is a very different test from CDM, and produces different information. Some background on the setup and information generated from the two testing methods will explain the differences. Then the role of VF-TLP in testing devices for CDM operation can be understood.
TLP is not a qualification test, but a characterization method. There is no standard stress level of TLP that is used as an IC classification. TLP can provide a current failure level, and much more information. The TLP test result is a pulsed I-V chart of current vs. voltage for a particular pin pair and polarity. From the TLP generated I-V graph the operation of the ESD protection at very short time frames and high currents can be understood in detail. The series of increasing pulses maps the device turn-on voltage, and if a snapback operation happens, that is clear. The on resistance is traced and details such as triggering of individual FET fingers, heating effects and voltage breakdowns can be seen if present. At current levels up to many amperes the operation is mapped. Destructive current levels are verified using lower level DC curve tracing which can often detect smaller changes and physical damage. TLP rectangular pulses with 100 ns duration often correlate well with HBM testing. It was initially hoped that the very short VF-TLP pulses of 1 to 10 ns duration would correlate with CDM, but that has not been shown to be the general case.
TLP-CDM difference summary
One or two pins
A major difference between TLP and CDM is the current path through the DUT. TLP injects current into one pin with a ground current return path defined by a contact with a second pin. CDM produces a spark to one pin with a capacitive path to ground to the entire substrate. The CDM current spreads into the DUT substrate. The current path, and hence the impedance along the path, can be remarkably different if the TLP ground path is to a Vss pin, Vdd pin, or an I/O pin. There is no TLP path that can replicate the CDM current paths.
Precharged to a voltage vs. current pulse
The CDM stress is a discharge from a precharged condition specified by the voltage differential driving the discharge. TLP drives a pulse down a cable to the DUT, and the DUT impedance between the two pin will determine the current and voltage when a reflection is generated when the pulse impacts upon the DUT.
The TLP system typically has a 50-ohm delivery impedance. Practically, this means the DUT stress current will always equal the voltage difference between the two stress pins divided by 50. CDM stress impedance is dominated by the spark resistance between the ground discharge pin and the DUT pin. While this impedance is not controlled, and can vary with the atmosphere conditions (temperature and humidity especially) spark gap length, etc., and changes during the pulse.
Stress pulse rise time and duration
TLP has the advantage of a carefully crafted pulse. The pulse width can be changed as can its rise time. CDM, on the other hand, is dominated by the capacitance of the DUT to the reference planes of the tester (upper ground plate and lower field charge plate) and the type of pin being tested. The CDM pulse width can vary from less than a half nanosecond to over a nanosecond, even between pins of the same part. Legacy VF-TLP systems have minimum pulse widths of 1 t o1.25 ns, while GTS offers a UF-TLP system with 0.5, 1 and 2 ns pulse widths. Studies have mapped CDM current differences between pins at the center of the DUT versus the edge. TLP scans the DUT operation over a large range of voltage/current but there is no way to directly match the CDM current at a specific pin.
VF-TLP verifying design models
If VF-TLP doesn’t replicate the CDM stress, why is VF-TLP used to test CDM protection structures? Because it provides operational information that can’t otherwise be measured. The fast rise time of VF-TLP can meet, and even exceed, the CDM rise time. The detailed scanning of high resolution pulse amplitude provides the clamping capability, on resistance measurements and determination of power dissipation limitations.
The measurement of a circuit response from a high current pulse within a nanosecond can verify that design is correct. And if the performance isn’t what the simulation showed then corrections can be made.